1. Field of the Invention
The invention relates generally to post-processing with heat of focused ion beam deposited “metal lines” or layers, and the resultant reduction of the metal line or layer's electrical resistance.
2. Background
Integrated circuit structures are generally formed of numerous discrete devices on a semiconductor chip such as a silicon semiconductor chip. The individual devices are interconnected in appropriate patterns to one another and to external devices through the use of interconnection lines or interconnects to form an integrated device. Typically, many integrated circuit devices are formed on a single structure, such as a wafer substrate and, once formed, are separated into individual chips or dies for use in various environments.
There are several conventional processes for introducing metals such as aluminum, an aluminum alloy, or platinum to form an interconnect onto a substrate. The metal is generally introduced in the form of a deposition process, (e.g., chemical vapor deposition (CVD)) and patterned by way of an etching process into a discrete line or lines. Another process for introducing a metal interconnect, particularly copper or its alloys over a substrate is the damascene process. The damascene process introduces copper interconnect according to a desired pattern previously formed in dielectric material over a substrate.
Yet another process is FIB metal deposition that is generally used to introduce thin metal lines or arbitrary patterns as a layer over a substrate. FIB deposition is used for modification of small metallic structures such as the modification of existing interconnects in integrated circuits. In the FIB, a gaseous metal-organic precursor containing metal (e.g. platinum, tungsten etc.) is introduced over a substrate. The ion beam contacts the gaseous metal-organic precursor causing the dissociation of the precursor and the release of metal atoms. The metal atoms then form a metal line or layer over the substrate.
One disadvantage of FIB metal line deposition is that the material that is formed is impure, and typically has a high (in comparison to process lines) electrical resistance such as 160 micro Ohm centimeters (micro Ohm cm) to 200 micro Ohm cm. What is needed is a process and a tool that allows for the introduction of metals to form a layer over a substrate that is both efficient and decreases the electrical resistance of the FIB interconnect.